1. Field of the Invention
This invention relates generally to boundary scan testing of interconnections between integrated circuits.
2. Description of the Related Art
Electronic systems generally include one or more printed circuit boards (PCB's) and one or more integrated circuit chips (IC chips). IC chips typically include input/output pins (I/O pins) which may be coupled to interconnects of a PCB. Testing performance of electronic systems which include PCB's and IC chips typically requires testing at chip level, at board level, and at system level. Testing at board level includes testing interconnects of the PCB. Testing at system level requires analysis of interconnections between IC chips, PCB's, and other devices.
To enhance testability at board level as well as at system level, a common design practice at chip level is to incorporate boundary scan test logic an IC in accordance with IEEE Standard 1149.1. IEEE standard 1149.1 specifies the function of JTAG logic, which is named for the Joint Test Action Group (JTAG), for control of boundary scan testing.
FIG. 1A is a conceptual block diagram of an integrated circuit chip (IC chip) 100. In accordance with IEEE standard 1149.1, prior art boundary scan cells 102 are inserted between core logic 104 and input/output pins (I/O pins) 106 of IC 100. Boundary scan cells 102 are typically inserted for all I/O pins 106 of a plurality of IC chips 100 and may be used to test the integrity of interconnections (not shown) between a plurality of IC chips such as IC chip 100.
IC chip 100 may be controlled by boundary scan logic, in accordance with IEEE standard 1149.1, to operate in a system mode or in a JTAG test mode. In the system mode, system data signals relating to core functions of IC chip 100 are passed through I/O pins 106 to and from devices external to IC chip 100. In the JTAG test mode, test data are provided by the boundary scan chain for the purpose of testing interconnections between IC chip 100 and devices external to IC chip 100. The boundary scan logic also provides test control signals which include mode signals, shift signals, clock signals, and update signals each of which is described below. Shift control signal instructions include a bypass instruction, a sample instruction, and a cross test instruction. The cross test instruction controls boundary scan cells 102 to perform a boundary scan test among IC chips such as IC chip 100.
IC chip 100 further includes a test data input demultiplexer (TDI demultiplexer) 108, a test data output (TDO) multiplexer 110, a bypass register 112, an instruction register 114, an identification register 116, and a TAP controller 118. TDI demultiplexer 108 includes an input 109 coupled to receive a test data signal from boundary scan logic (not shown) which is typically external to IC 100. TDI demultiplexer 108 includes a first output coupled to a test data input (TDI input) of a first boundary scan cell of boundary scan cells 102. Each of boundary scan cells 102 includes a test data input (TDI input) and a test data output (TDO output). Each of boundary scan cells 102 is connected serially from a TDO output to a TDI input to propagate test data signals as is described further below. TDI demultiplexer 108 further includes a second output coupled to an input of core logic 104, a third output coupled to an input to bypass register 112; a fourth output coupled to an input of instruction register 114; and a fifth output coupled to an input of identification register 116.
TDO multiplexer 110 includes an output 111 which is coupled to provide a test data signal to another IC chip 100 or to boundary scan logic. TDO multiplexer 110 further includes: a first input coupled to a TDO output of a boundary scan cell of boundary scan cells 102, a second input coupled to an output of core logic 104; a third input coupled to an output of bypass register 112; a fourth input coupled to an output of instruction register 114, and a fifth input coupled to an output of identification register 116. Identification register 116 includes inputs coupled to outputs of tap controller 118. Tap controller 118 includes inputs coupled to receive a TMS signal, a TCK signal, and a TRST signal from the boundary scan logic.
FIG. 1B is a conceptual block diagram of input/output structures (I/O structures) in an integrated circuit including a two-state I/O structure 120, a three-state I/O structure 130, and a bidirectional I/O structure 140. Each of state I/O structures 120, 130, and 140 provides coupling between core logic 104 and an I/O pin of I/O pins 106.
Two-state I/O structure 120 includes a two-state output buffer 122. A two-state front end system data net 124 provides coupling between a system data output of core logic 104 and an input 122a of two-state output buffer 122. A two-state back end system data net 126 provides coupling between an output 122b of two-state output buffer 122 and an I/O pin of I/O pins 106.
Three-state I/O structure 130 includes a three-state output buffer 132. A three-state front end system data net 134 provides coupling between a system data output 104b of core logic 104 and an input 132a of three-state output buffer 132. A three-state back end system data net 136 provides coupling between an output 132b of three-state output buffer 132 and an I/O pin of I/O pins 106. A three-state control net 138 provides coupling between a three-state system control signal output line 104c of core logic 104 and a control input 132c of three-state output buffer 132.
Bidirectional I/O structure 140 includes a bidirectional buffer 142. Bidirectional buffer 142 includes an output buffer element 144 and an input buffer element 146. A bidirectional control net 148 provides coupling between a bidirectional control signal output line 104d of core logic 104 and a control input 144a of output buffer element 144. A bidirectional front end system data net 150 provides coupling between a system data output 104e of core logic 104 and an input 144a of output buffer element 144. A bidirectional input data net 152 provides coupling between an output 146a of input buffer element 146 and a system data received input 104f of core logic 104. A bidirectional back end system data net 154 provides coupling between an output 144c of output buffer element 144 and an I/O pin of I/O pins 106. Input buffer element 146 includes an input 146b coupled to bidirectional back end system data net 154.
FIG. 1C shows a conceptual block diagram of the input/output structures of FIG. 1B with prior art boundary scan cells inserted therein. According to prior art methods and apparatus for boundary scan testing, prior art boundary scan cells are inserted into the I/O structures 120, 130, and 140 of FIG. 1B by bisecting each front end system data net 124, 134, 150, 152 and each control net 138, 148 (FIG. 1B).
A prior art boundary scan cell (BSC) 160a is inserted into two-state output structure 120a, between core logic 104 and input 122a of three-state output buffer 122. This insertion is accomplished in the prior art by bisecting of two-state front end system data net 124 resulting in a first two-state split system data net 124a and a second two-state split system data net 124b (FIG. 1C). First two-state split system data net 124a provides coupling between a system signal input 161 of a prior art BSC 160a and system data output 104a of core logic 104. Second two-state split system data net 124b provides coupling between a system output 162 of prior art BSC 160a and input 122a of two-state output buffer 122.
Prior art BSC 160 includes a system input line 161 for receiving system signals including system data signals and system control signals from system signal output lines, including system data signal output lines and system control signal output lines, of core logic 104. If BSC 160 is used for control purposes, system input 161 may receive a system control signal from core logic 104. If BSC 160 is used for output, system input line 161 may receive a system data signal from core logic 104. BSC 160 also includes: a system output 162; a test data input (TDI) line 163 which may receive a test data signal from boundary scan logic either directly or via another boundary scan cell; and a test data output (TDO) line 164 for providing test data to boundary scan logic either directly or via another boundary scan cell. BSC 160 further includes a JTAG input 165 which is described further below. BSC's 160a, 160b, 160c, and 160d of FIG. 1C are each identical to BSC 160.
A prior art BSC 160c is inserted into three-state output structure 130a, between system data output 104c of core logic 104 and input 132a of three-state output buffer 132. This insertion is accomplished in the prior art by bisecting three-state system data net 134 (FIG. 1B) resulting in first three-state split system data net 134a and a second three-state split system data net 134b (FIG. 1C). First two-state split system data net 134a provides coupling between system data output 104b of core logic 104 and system input 161 of BSC 160c. Second three-state split system data net 134b provides coupling between a system output 162 of BSC 160c and input 132a of three-state output buffer 132. BSC 160c serves as an output boundary scan cell in three-state output structure 130. System output 162 of BSC 160c provides a system data signal to an I/O pin of I/O pins 106 via three-state split system data net 134b.
A prior art BSC 160b is inserted into three-state output structure 130a between three-state control signal output line 104c of core logic 104 and control input 132c of three-state output buffer 132. This insertion is accomplished in the prior art by bisecting three-state control net 138 (FIG. 1B) resulting in a first three-state split control net 138a and a second three-state split control net 138b (FIG. 1C). First three-state split control net 138a provides coupling between system input 161 of prior BSC 160b and two-state control signal output line 104c of core logic 104. Second three-state split system data net 138b provides coupling between system output 162 of prior BSC 160b and control input 132c of three-state output buffer 132. Prior art BSC 160b serves as a control boundary scan cell in three-state output structure 130a.
A BSC 160d is inserted into bidirectional output structure 140b, between system control signal output line 104d of core logic 104 and prior art bidirectional output buffer 142. This insertion is accomplished in the prior art by bisecting bidirectional control net 148 (FIG. 1B) resulting in a first split bidirectional control net 148a and second split bidirectional control net 148b (FIG. 1C). First split bidirectional control net 148a provides coupling between system control signal output line 104d of core logic 104 and system input 161 of BSC 160d. Second split bidirectional control net 148b provides coupling between system output 162 of BSC 160d and control input 144c of output buffer element 144. Prior art BSC 160d serves as a control boundary scan cell in bidirectional output structure 140b.
A prior art bidirectional boundary scan cell (prior art bidirectional BSC) 180 is inserted into bidirectional output structure 140 between core logic 104 and prior art bidirectional output buffer 142. This insertion is accomplished in the prior art by bisecting bidirectional output data net 150 and bidirectional input data net 152 (FIG. 1B). Bisecting bidirectional output data net 150 and bidirectional input data net 152 results in a first bidirectional split output data net 150a, a second bidirectional split output data net 150b, a first bidirectional split input data net 152a, and a second bidirectional split input data net 152b (FIG. 1C).
First bidirectional split output data net 150a provides coupling between system data output 104e of core logic 104 and a system data input 181 of prior art bidirectional BSC 180. Second bidirectional split output data net 150b provides coupling between a system data output 182 of prior art bidirectional BSC 180 and input 144b of bidirectional output buffer element 144. First bidirectional split input data net 152a provides coupling between system data received input 104f of core logic 104 and a system data received output 183 of prior art bidirectional BSC 180. Second bidirectional split input data net 152b provides coupling between a system data received input 184 of prior art bidirectional BSC 180 and output 146a of input buffer element 146.
Inserting boundary scan cells 160a-160d, and 180 into the I/O structures 120, 130, and 140 of FIG. 1B impacts the timing characteristics of each of I/O structures 120, 130, and 140 while each of I/O structures 120, 130, and 140 operate in the system mode. Specifically, inserting boundary scan cells 160a-160d, and 180 into the I/O structures 120, 130, and 140 introduces a time delay for signals propagating between core logic 104 and buffers 122, 132, and 142. This time delay problem is further described below. Also, the splitting of each of front end system data nets 124, 134, 150, 152 makes wire estimation difficult in synthesis without layout information and also makes layout difficult to meet system timing requirements as each of the split nets may be critical for layout and design.
FIG. 1D is a conceptual block diagram of a four-bit three-state output structure 130b without boundary scan cells inserted therein. Four-bit three-state output structure 130b includes four three-state output buffers 132f, 132g, 132h, and 132i. Each of three-state output buffers 132f, 132g, 132h, and 132i has an input 132a coupled respectively to receive a system data output signal from a system data output 104c1, 104c2, 104c3, and 104c4 of core logic 104. A three-state control net 138 provides coupling between control signal output line 104b of core logic 104 and a control input 132c of each of three-state output buffers 132f, 132g, 132h, and 132i.
FIG. 1E is a conceptual block diagram of a four-bit three-state output structure 130c with prior art output boundary scan cells inserted therein. BSC's 160f, 160g, 160h, and 160i are inserted respectively between system data output lines 104c1, 104c2, 104c3, and 104c4 of core logic 104 and input 132a of prior art three-state output buffers 132f, 132g, 132h, and 132i. This insertion is accomplished in the prior art by bisecting each three-state system data net 134 (FIG. 1D) resulting in a first three-state split system data net 134a and a second three-state split system data net 134b (FIG. 1E) for each of BSC's 160f, 160g, 160h, and 160i. Each first two-state split system data net 134a provides coupling respectively between a system input 161 of a BSC 160f, 160g, 160h, and 160i and a system data output 104c1, 104c2, 104c3, and 104c4 of core logic 104. Second three-state split system data net 134b provides coupling respectively between a system output 162 of BSC 160f, 160g, 160h, and 160i and input 132a of three-state output buffers 132f, 132g, 132h, and 132i. System output 162 of BSC 160e is loaded by four prior art three-state output buffers 132f, 132g, 132h, and 132i. A problem arises in the prior art due to this excessive loading.
As shown in FIG. 1D, 104b is a driver that provides sufficient drive for driving a 4 bit bus. Consequently, when the design is modified to include the BSC logic as shown in FIG. 1E, the driver 104b will necessarily be optimized with more drive than is actually needed, and therefore, resources will be wasted. For example, the drive provided by driver 104 in FIG. 1D included a number of buffers (not shown) that are constructed from many transistor gates, which has a down side of occupying more chip space. It should therefore be appreciated that the prior art design of FIG. 1E is not optimized when the BSC 160e is added.
Another problem that arises when BSC 160e is added in FIG. 1E, is that the output of BSC 160e will not have the same drive strength provided by driver 104b. Therefore, BSC 160e will not be able to drive additional bits that may be required in a particular design. By way of example, BSC 160e may be able to drive 4 bits, but if additional bits are added to a design, the BSC 160e will not be able to handle the new drive requirements. To overcome this problem, chip designers have included an additional buffer at the output of the BSC 160e, however, this has the detrimental effect of introducing additional delay.
A further problem with the prior art technique of inserting BSC's is that the nets 138, and 134 must be broken into two nets (i.e., 138a/138b and 134a/134b), which necessarily increases the number of nets in a design. When happens, it will be more difficult to meet the timing requirements of a particular design. Furthermore, it is usually desired to place the BSC's closer to the output buffers 132, however, this would require a substantial amount of manual labor to individually place each BSC close to each of the output buffers 132.
FIG. 1F is a conceptual block diagram of a four-bit bi-directional I/O structure 140c which includes four prior art bidirectional buffers 142a, 142b, 142c, and 142d. Bidirectional control net 148 provides coupling between a control output line 104d of core logic 104 and a control input 144a of output buffer element 144 of each bidirectional buffer 142a, 142b, 142c, and 142d. Bidirectional front end system data nets 150 provide coupling respectively between a system data output 104e1, 104e2, 104e3, and 104e4 of core logic 104 and input 144b of output buffer element 144 of each of bidirectional buffers 142a, 142b, 142c, and 142d. Bidirectional input data nets 152 provides coupling respectively between output 146a of input buffer element 146 of each of bidirectional buffers 142a, 142b, 142c, and 142d and system data received input 104f1, 104f2, 104f3, and 104f4 of core logic 104.
FIG. 1G is a conceptual block diagram of a four-bit bi-directional I/O structure 140d with prior art bi-directional output boundary scan cells inserted therein. Also shown are a plurality of prior art bidirectional boundary scan cells (prior art bidirectional BSC) 180.
A control BSC 160j is inserted into bidirectional output structure 140d, between control signal output 104d of core logic 104 and prior art bidirectional buffer 142a, 142b, 142c, and 142d (FIG. 1F). This insertion is accomplished in the prior art by bisecting bidirectional control net 148 resulting in a first split bidirectional control net 148a and second split bidirectional control net 148b. First split bidirectional control net 148a provides coupling between control data output 104d of core logic 104 and a system input 161 of BSC 160j. Second split bidirectional control net 148b provides coupling between system output 162 of BSC 160j and control input 144a of output buffer element 144 of prior art bidirectional buffer 142a, 142b, 142c, and 142d.
Prior art bidirectional boundary scan cells (prior art bidirectional BSC's) 180b, 180c, 180d, and 180e are inserted respectively between core logic 104 and bidirectional buffers 142a, 142b, 142c, and 142d. First bidirectional split output data nets 150a provide coupling respectively between system a data output 104e1, 104e2, 104e3, and 104e4 of core logic 104 and a system data input 181 of bidirectional BSC's 180b, 180c, 180d, and 180e. Second bidirectional split output data nets 150b provide coupling respectively between system data output 182 of bidirectional BSC's 180b, 180c, 180d, and 180e and input 144b of a bidirectional output buffer element 144 of a bidirectional output buffers 142a, 142b, 142c, and 142d.
First bidirectional split input data nets 152a provide coupling respectively between a system data received input 104f1, 104f2, 104f3, and 104f4 of core logic 104 and a system data received output 183 of bidirectional BSC's 180b, 180c, 180d, and 180e. Second bidirectional split input data nets 152b provide coupling respectively between a system data received input 184 of bidirectional BSC's 180b, 180c, 180d, and 180e and an output 146a of an input buffer element 146 of a bidirectional output buffer 142a, 142b, 142c, and 142d.
FIG. 2 is a detailed logic block diagram of prior art BSC 160. Prior art BSC 160 includes system data input line 161 for receiving a system data signal or a system control signal from core logic 104 (FIG. 1A). Prior art BSC 160 also includes BSC output line 162, test data input (TDI) line 163, and test data output (TDO) line 164.
Prior art BSC 160 further includes a JTAG input 165. JTAG input 165 includes a mode signal input line 202, a shift signal input line 204, a clock signal input line 206, and an update signal input line 208. Mode input line 202 is coupled to receive a mode signal from boundary scan logic via JTAG bus 105. Shift signal input line 204 is coupled to receive a shift signal from boundary scan logic via JTAG bus 105. Clock signal input line 206 is coupled to receive a clock signal from boundary scan logic via JTAG bus 105. Update signal input line 208 is coupled to receive an update signal from boundary scan logic via JTAG bus 105.
Prior art BSC 160 includes a boundary scan mode multiplexer (mode multiplexer) 220, a shift multiplexer 230, a data shift register 240, and an update data register 250. Mode multiplexer 220 further includes a system input 222, an update input 224, an output 226, and a control line 228. System input 222 of mode multiplexer 220 is coupled to receive a system signal via system input line 161. Update input 224 of mode multiplexer 220 is coupled to receive a signal from an inverted output 256 of update data register 250. Output 226 of mode multiplexer 220 is coupled to provide an output signal to BSC output line 162.
With reference back to FIG. 1E, system output 162 of BSC 160e is loaded by four prior art three-state output buffers 132f, 132g, 132h, and 132i when BSC 160e is used for control BSC. A problem arises in the prior art due to this excessive loading. Because output 226 of mode multiplexer 220 is coupled to provide an output signal to BSC output line 162, output 226 of mode multiplexer 220 may be excessively loaded in the case of four-bit three-state output structure 130c of FIG. 1E. Due to the multiplexer 220, there is one mux-delay in system mode.
Control line 228 of mode multiplexer 220 is coupled to receive a mode signal via mode signal input line 202. As mentioned above, BSC mode multiplexer 220 introduces a one-multiplexer time delay for signals propagating between core logic 104 and buffers 122, 132, and 142. Prior art shift multiplexer 230 includes a system input 232, a test data input 234, an output 236, and a control line 238. System input 232 is coupled to receive a system signal via system input line 161. Test input 234 is coupled to receive a test data signal via TDI line 163. Output 236 is coupled to provide a signal to a data input 242 of prior art data shift register 240. Control line 238 is coupled to receive the shift signal via shift signal input line 204. Data shift register includes a data input 242, a clock input 244, a normal output 246, and an inverted output 248. Clock input 244 of data shift register 240 is coupled to receive a clock signal via clock signal input line 206. Normal output 246 of data shift register 240 is coupled to provide a test data signal to TDO line 164. Inverted output 248 is coupled to provide a signal to a data input line 252 of update data register 250. Update data register 250 includes a data input 252, a toggle input 254, and an inverted output 256. Update input 254 is coupled to receive an update signal via update signal input line 208.
FIG. 3 is a detailed logic block diagram of a prior art bi-directional boundary scan cell (prior art bi-directional BSC) 180. As described above, prior art bidirectional BSC 180 includes a system data input line 181, a system data output line 182, system data received output 183, a system data received input 184, a test data input (TDI) line 185, a test data output (TDO) line 186, and a JTAG input 187. System data received output 183 is coupled to system data output line 182. JTAG input 187 includes a shift signal input line 302, a clock signal input line 304, and an update signal input line 306. Shift signal input line 302 is coupled to receive a shift signal from boundary scan logic via JTAG bus 105. Clock data input line 304 is coupled to receive a clock signal from boundary scan logic via JTAG bus 105. Update signal input line 306 is coupled to receive an update signal from boundary scan logic via JTAG bus 105. Prior art bidirectional BSC 180 includes a bidirectional system multiplexer 320, a direction control multiplexer 330, a bidirectional shift control multiplexer 340, a bidirectional data shift register 350, and a bidirectional update data register 360.
A system data input 322 of bi-directional system multiplexer 320 is coupled to receive a system data signal via system data input 181 of prior art bidirectional BSC 180. An update input 324 of bidirectional system multiplexer 320 is coupled to receive a signal from an inverted output 366 of bidirectional update data register 360. An output 326 of bi-directional system multiplexer 320 is coupled to provide a signal to system data output line 182 of prior art bidirectional BSC 180.
A system data input 332 of direction control multiplexer 330 is coupled to receive a system data signal via system data input line 181 of bidirectional BSC 180. A system data received input 334 of direction control multiplexer 330 is coupled to receive the system data received signal via system data received input 184 of prior art bidirectional BSC 180. An output 336 of direction control multiplexer 330 is coupled to provide a signal to a data input 342 of bidirectional shift control multiplexer 340. A control line 338 of direction control multiplexer 330 is coupled to receive a directional control signal via direction control input 188.
A test data input (TDI) 344 of bidirectional shift control multiplexer 340 is coupled to receive a test data signal via TDI input 185 of prior art bidirectional BSC 180. An output 346 of bidirectional shift control multiplexer 340 is coupled to provide a signal to a data input 352 of bidirectional data shift register 350. A control line 348 of bidirectional shift control multiplexer 340 is coupled to receive a shift signal via shift signal input line 302 of prior art bidirectional BSC 180. A clock input 354 of bi-directional data shift register 350 is coupled to receive a clock signal via clock signal input 304 of prior art bidirectional BSC 180. A normal output 356 of bi-directional data shift register 350 is coupled to provide a test data out signal to TDO output 186 of prior art bidirectional BSC 180. An inverted output 358 of bi-directional data shift register 350 is coupled to provide a signal to a data input 362 of bi-directional update data register 360. An update input 364 of bi-directional update data register 360 is coupled to receive an update signal via update input 306 of prior art bidirectional BSC 180.
With reference back to FIG. 1C, inserting boundary scan cells 160, 170, and 180 into the I/O structures 120, 130, and 140 introduces a time delay for signals propagating between core logic 104 and buffers 122, 132, and 142. With reference to FIGS. 2 and 3, it can be seen that the time delay introduced in each case is a one-multiplexer time delay.
What is needed is a method and apparatus for insertion of boundary scan test logic into cells of an integrated circuit such that no splitting of front end system data interconnects is required for insertion of boundary scan cells. What is also needed is a method and apparatus for insertion of boundary scan cells into an integrated circuit wherein timing delays associated with multiplexers in boundary scan cells may be alleviated. What is further needed is a method and apparatus for insertion of boundary scan cells into an integrated circuit wherein problems associated with layout and wire estimation in synthesis and timing analysis may be alleviated.